SRAM Design-ed

SRAM Design usually consists of one or more rectangular arrays of memory cells with support circuitry to decode addresses, which implement the required read and write operations. The total size of the memory, the speed at which the memory must operate, layout and testing requirements, and the number of data I/Os on the chip determine the number of arrays on a memory chip. Each SRAM memory cell consists of a bi-stable flip-flop. The flip-flop is usually made up of four to six transistors and may be in either of two states that can be interpreted by the support circuitry to be a 1 or a 0.

The SRAM memory arrays are arranged in rows and columns of memory cells. The rows are referred to as wordlines and the columns as bitlines. Each memory cell has its own unique location or address, which is defined by the intersection of a row and column. Each memory cell's location is linked to a particular data input/output pin.

Most SRAMs use a four transistor cell with a polysilicon load. Such SRAMs with four transistor cell are ideal for medium to high performance. However, the four transistor cell design has a relatively high leakage current. This also means SRAMs consume a high amount of power during standby mode. Four transistor designs are also said to exhibit various types of radiation induced soft errors. Some SRAMs use a six transistor memory cell. These devices are said to be highly stable and are usually not prone to soft errors. They also have low leakage and standby current consumption.

Parts from USBid:
74F367J
2725501
2SA1523-AC
1206J6K8
TSW10706TD